| Relevance of Course Objectives and Core Learning Outcomes(%) |
Teaching and Assessment Methods for Course Objectives |
| Course Objectives |
Competency Indicators |
Ratio(%) |
Teaching Methods |
Assessment Methods |
You are expected to achieve the following capabilities after taking this course
- proficiency in digital designs using HDL
- understanding how the logic synthesis works
- correctly writing the synthesizable code and interpreting the synthesis result |
|
|
| Exercises |
| Discussion |
| Practicum |
| Lecturing |
|
| Assignment |
| Quiz |
| Internship |
|
| Course Content and Homework/Schedule/Tests Schedule |
| Week |
Course Content |
| Week 1 |
Overview of digital design with HDL |
| Week 2 |
Review of logic design basics |
| Week 3 |
Hierarchical modeling and Basic concepts |
| Week 4 |
- language basics of Verilog
- simulation tool: modelsim |
| Week 5 |
Data flow modeling |
| Week 6 |
Behavioral Modeling |
| Week 7 |
Design examples |
| Week 8 |
Advanced coding techniques |
| Week 9 |
midterm exam |
| Week 10 |
Timing modeling and Verification |
| Week 11 |
Case studies |
| Week 12 |
Synthesizable coding |
| Week 13 |
Logic synthesis flow |
| Week 14 |
Logic synthesis constraints |
| Week 15 |
logic synthesis report |
| Week 16 |
coding guidelines (1) |
| Week 17 |
coding guidelines (2) |
| Week 18 |
final exam |
|
| Evaluation |
- Homework’s (written + simulation) 30%
- HDL simulation tool proficiency test (on computer) 10%
- Midterm exam (written) 25%
- Final exam (written + on computer) 35%
|
| Textbook & other References |
| Samir Palnitkar, "Verilog HDL – A Guide to Digital Design and Synthesis," 2nd edition, Prentice Hall, 2005 |
| Teaching Aids & Teacher's Website |
| - visit the NCHU iLearnig3 site |
| Office Hours |
| arranged by e-mail |
| Sustainable Development Goals, SDGs |
| | include experience courses：N |
|