| 課程與核心能力關聯配比(%) |
課程目標之教學方法與評量方法 |
| 課程目標 |
核心能力 |
配比(%) |
教學方法 |
評量方法 |
You are expected to achieve the following capabilities after taking this course
- proficiency in digital designs using HDL
- understanding how the logic synthesis works
- correctly writing the synthesizable code and interpreting the synthesis result |
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| 授課內容(單元名稱與內容、習作/每週授課、考試進度-共18週) |
| 週次 |
授課內容 |
| 第1週 |
Overview of digital design with HDL |
| 第2週 |
Review of logic design basics |
| 第3週 |
Hierarchical modeling and Basic concepts |
| 第4週 |
- language basics of Verilog
- simulation tool: modelsim |
| 第5週 |
Data flow modeling |
| 第6週 |
Behavioral Modeling |
| 第7週 |
Design examples |
| 第8週 |
Advanced coding techniques |
| 第9週 |
midterm exam |
| 第10週 |
Timing modeling and Verification |
| 第11週 |
Case studies |
| 第12週 |
Synthesizable coding |
| 第13週 |
Logic synthesis flow |
| 第14週 |
Logic synthesis constraints |
| 第15週 |
logic synthesis report |
| 第16週 |
coding guidelines (1) |
| 第17週 |
coding guidelines (2) |
| 第18週 |
final exam |
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| 學習評量方式 |
- Homework’s (written + simulation) 30%
- HDL simulation tool proficiency test (on computer) 10%
- Midterm exam (written) 25%
- Final exam (written + on computer) 35%
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| 教科書＆參考書目(書名、作者、書局、代理商、說明) |
| Samir Palnitkar, "Verilog HDL – A Guide to Digital Design and Synthesis," 2nd edition, Prentice Hall, 2005 |
| 課程教材（教師個人網址請列在本校內之網址） |
| - visit the NCHU iLearnig3 site |
| 課程輔導時間 |
| arranged by e-mail |
| 聯合國全球永續發展目標(連結網址) |
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