| 課程與核心能力關聯配比(%) |
課程目標之教學方法與評量方法 |
| 課程目標 |
核心能力 |
配比(%) |
教學方法 |
評量方法 |
| This course is designed to give you a comprehensive coverage of the VLSI architectures for digital signal processing. The main theme of the course is to design efficient VLSI architectures for computing algorithms frequently encountered in DSP systems. In other words, this course will teach you how to map DSP algorithms onto VLSI. |
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| 授課內容(單元名稱與內容、習作/每週授課、考試進度-共18週) |
| 週次 |
授課內容 |
| 第1週 |
introduction to VLSI digital signal processing |
| 第2週 |
review of DSP algorithms |
| 第3週 |
review of DSP algorithms |
| 第4週 |
algorithm representations and iteration bound |
| 第5週 |
algorithm representations and iteration bound |
| 第6週 |
mapping algorithms onto array structures |
| 第7週 |
mapping algorithms onto array structures |
| 第8週 |
QR factorization design example |
| 第9週 |
Mid term exam |
| 第10週 |
retiming scheme |
| 第11週 |
unfodling scheme |
| 第12週 |
folding scheme |
| 第13週 |
folding scheme |
| 第14週 |
pipelining and parallel processing for low power |
| 第15週 |
pipelined and parallel recursive and adaptive filters |
| 第16週 |
pipelined and parallel recursive and adaptive filters |
| 第17週 |
Deep learning architecture for CNN network |
| 第18週 |
final exam |
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| 學習評量方式 |
| homework assignments, mid term exam, final exam, term project |
| 教科書＆參考書目(書名、作者、書局、代理商、說明) |
| “VLSI Digital Signal Processing Systems – Design and Implementation,” by Keshab Parhi, John Wiley & Sons, 1999 |
| 課程教材（教師個人網址請列在本校內之網址） |
| iLearning Website |
| 課程輔導時間 |
| Wednesday 1-3PM |
| 聯合國全球永續發展目標(連結網址) |
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